1. Field of the Invention
This invention relates to a method of forming a pattern and to a method of manufacturing a semiconductor device. In particular, this invention relates to the formation of a fine pattern to be employed in the manufacture of a semiconductor device.
2. Description of the Related Art
In the process of manufacturing a semiconductor device, the technique of photolithography is widely employed as a method of forming a pattern on a semiconductor substrate.
Since the technique of photolithography is limited with regard to the pattern resolution as the resolution is determined by the wavelength of light due to diffraction, it is difficult to form such a fine pattern that is more minute than the aforementioned resolution limit which is demanded in conformity with the enhancement in integration of semiconductor device.
In view of this, there has been proposed a method of forming such a fine pattern that exceeds the aforementioned resolution limit to be determined by the wavelength of light even in the employment of photolithographic technique (see for example, U.S. Pat. No. 6,063,688 and U.S. Pat. No. 6,638,441).
According to the method of forming a pattern which is disclosed in U.S. Pat. No. 6,063,688, a first pattern of silicon nitride film is formed on the surface of substrate by means of photolithography, and then a first sidewall film of silicon oxide film is formed on the sidewalls of the first pattern, the first pattern being subsequently removed to form a second pattern of silicon oxide film. Thereafter, a second sidewall film of silicon nitride film is formed on the sidewalls of the second pattern, and then the second pattern is removed to form a fine third pattern having a pitch one fourth that of the first pattern.
Further, according to the method of forming a pattern which is disclosed in U.S. Pat. No. 6,638,441, a first pattern of resist film is formed on the surface of substrate by means of photolithography, a first sidewall film of dielectric material is formed on the sidewalls of the first pattern, and then the space between a pair of the resultant first dielectric sidewall films facing each other is filled with a polymer. Thereafter, the first pattern is removed to form a second pattern having a structure where the space between neighboring dielectric sidewall films is filled with the polymer. Then, a second sidewall film of polymer is formed on the sidewalls of the second pattern, and the space between a pair of the resultant sidewall films facing each other is filled with a dielectric film. Subsequently, the polymer is removed to obtain a state where a line of dielectric film is added to the second pattern, thereby forming a fine second pattern having a pitch of one third that of the first pattern.
The methods of forming a pattern disclosed in U.S. Pat. No. 6,063,688 and U.S. Pat. No. 6,638,441 however are accompanied with a problem that the number of steps is inevitably increased since these methods include a plurality of etching steps where the etching of film is required to be performed deep enough to reach the surface of substrate.
Furthermore, when a film is etched to a sufficient extent to reach and expose the surface of substrate, the exposed surface of substrate is inevitably etched more or less. As a result, a step is caused to be created on the surface of substrate, the magnitude of this step becoming more prominent as the number of etching steps increases, thus resulting in the creation of asymmetric step portions on the opposite sides of the line of pattern, thus raising problems.
As a result, when it is desired to form a fine pattern on a substrate by making use of such a fine pattern as a mask, the working precision may be caused to deteriorate due to the existence of such steps, thus badly affecting the characteristics of semiconductor device.
For example, when a gate electrode is formed by etching a gate electrode material layer by means of the RIE method using the aforementioned fine pattern as a mask, the portion of the gate insulating film located at a deepest portion of the step is caused to expose before the other portion of the gate insulating film is permitted to expose due to the asymmetric steps created on the surface of the gate electrode material layer.
Since the gate insulating film is required to be as very thin as about 1 nm in compliance with a trend to further miniaturize semiconductor device in recent years, the gate insulating film that has been exposed at first due to over-etching may be destroyed.